1. Technical Overview
The present invention relates to a semiconductor chip and a semiconductor device using the chip. More particularly, the present invention relates to a hybrid semiconductor device having a power portion coupled to a control portion which controls the power portion.
2. Related Art
The prior art includes structures which couple control IC's and power devices (such as IGBTs and the like) together in a single package or unit. Often, the control IC and the power IC require different manufacturing processes. This divergence in manufacturing processes often results in the control IC being manufactured separately from the power IC. Only after completion, the different devices are mounted on a glass epoxy substrate or on a ceramic substrate together with other passive devices (such as resistors, capacitors, and inductors). Alternatively, these devices are accommodated into a single package unit.
FIG. 6 shows an example of the hybrid type semiconductor device, which is formed on a glass epoxy substrate. In this formation, for example plural control-ICs 101 or power devices 102 are mounted on glass epoxy substrate 105 together with the other passive devices 103 and 104.
FIG. 7 shows an example of the hybrid type semiconductor device, which is formed on a thick ceramic substrate. In this formation, for example, plural control-ICs 201 or power chips 202 are mounted on thick ceramic substrate 204 together with the other passive devices 203. In particular, power chip 202 is mounted on the thick ceramic substrate 204 by means of heat sink 205. Bonding wire 206 connects an electrode (not shown) on power chip 202 to a wire (not shown) on thick ceramic substrate 204.
FIG. 8 shows an example of the hybrid type semiconductor device structure, which may be formed into one package unit. In this formation, for example, control chip 304 and power chip 305 are mounted on rivets 302 and 303 in lead frame 301, respectively. These chips 304 and 305 are accommodated in package 306. Also electrodes on the chips 304 and 305 are connected respectively to leads 308 and 309 in lead frame 301 by means of bonding wire 307.
While the above structures of FIGS. 6-8 isolate the control chips from the power chips, one drawback is that the total device size increases by the physical separation of the chips. Also, as the number of parts used in the total structure increase, the reliability and yield of the resulting device decrease as the probability that at least one part will fail increases. In other words, the increase in the number of parts causes the substrate or package size to increase. In addition to preventing miniaturization, the additional parts increase the amount of wiring, while decreasing the end device's reliability and the yield.
Another effect of the increase in the amount of wiring due to the increase in the number of parts is a deterioration in the anti-noise characteristics of the device. While deterioration of the anti-noise characteristics of the device may be rectified by providing, for example, a by-pass capacitor, adding a capacitor further increases the number of devices (which may not be directly a cause of noise) which, in turn, causes further problems such as increasing the size of the device or decreasing the end device's reliability.
Similar problems exist when combining two divergent systems such as a memory device and a controller for controlling the memory device. For example, a flash memory is generally formed of one process while a controlling circuit is formed through a different process. Accordingly, it is difficult to readily combine the two circuits onto a single chip as the processes for forming the different circuits may be incompatible.
One solution to minimizing the size of packages is to combine two device portions onto a single hybrid chip. For example, if a control device portion and a power device portion are formed by non-conflicting processes, enabling different functions on one integrated chip (for example, low voltage control compared to high current modulation), then a hybrid chip may be produced.
FIG. 9 shows a hybrid chip structure. In this structure, control and power device portions 402 and 403 are formed in an array and integrated on chip 401. Insulating layer 404 separates chip substrate 401, device portion 402, and device portion 403.
While the structure of the hybrid chip of FIG. 9 is compact, there is a high possibility for detrimental fluctuations in the device characteristics and the chip rack due to excess heat. In particular, the side by side nature of the two devices enlarges the size of the resulting device while not correspondingly increasing the device's heat dissipating ability. Thus, because this structure integrates device portions in an array on a chip, the chip may easily suffer heat stress as the device's size increases. Accordingly, resulting problems include the total device size increasing while degrading reliability, even in the case where a hybrid semiconductor device is formed by employing an integrated chip, in which device portions are integrated in an array on the chip.
As described above, problems arise when conventional devices are combined such as when the sizes of the devices increase, the reliability decreases. Thus, an object of the present invention is to provide a hybrid semiconductor device, which may be miniaturized and still obtain a high reliability.